1. Field of the Invention
This invention relates to a circuit architecture that maps an internal address space into an external address space, where the mapping adapts according to the application of the circuit and according to a current operating mode of the circuit.
2. Description of Related Art
Many digital circuits access memory and other resources using addresses that identify an accessible source or destination of a digital signal. The addresses that uniquely identify the accessible sources and destinations for signals can be referred to as the external address space for the circuit. For large external address spaces, the number of address bits required to uniquely identify a specific source or destination can be relatively large. Typically, the circuit requires address buses, address registers, and associated logic having sufficient width to access any location in the local external address space. Thus, making a circuit having a large external address space increases circuit area, complexity, and cost.
To reduce the number of address bits used in a circuit, the external address space can be divided into pages with only one page being accessed at a time, and the circuit can use an internal address space that is sufficient to identify a storage location within a current page. Thus, most address buses, registers, and logic in the circuit can be limited to the number of bits required to uniquely identify a location in a page. Such circuits additionally require page selection logic, which selects the current page for accessed, but the circuit area of the page selection logic is often less than circuit area saved by the reduction in the number of address bits handled elsewhere in the circuit. Thus, a paged external address space or memory can reduce the overall circuit size and cost.
A disadvantage of a paged external address space is that not all addresses are simultaneously accessible, and accessing required information may require frequent page changes. Such page changes can slow memory access and reduce performance of a circuit. A memory architecture is desired that minimizes the number of address bits required for the internal address space of a circuit, is compatible with a large external address space, and does not require frequent page changes to locate required information.